Conventionally, a semiconductor chip is usually mounted on a lead frame serving as a chip carrier to form a semiconductor package. The lead frame comprises a die pad and a plurality of leads surrounding the die pad, such that the chip is attached to the die pad and is electrically connected to the leads via a plurality of bonding wires. And an encapsulant is formed to encapsulate the chip, the die pad, the bonding wires, and inner portions of the leads. This completes the semiconductor package with the lead frame.
There have been developed various types of semiconductor packages using lead frames as chip carriers, such as quad flat package (QFP), quad-flat non-leaded (QFN) package, small outline package (SOP), and dual in-line package (DIP), etc. In order to improve the heat dissipating efficiency and satisfy the size requirement of a small chip scale package (CSP), the QFN package with a die pad having an exposed bottom surface or an exposed-pad semiconductor package has become a mainstream package structure.
Moreover, for further improving the electrical performances of the conventional lead-frame-based semiconductor package, besides electrically connecting the semiconductor chip to the leads via signal wires, ground pads on the chip can be electrically connected to the die pad of the lead frame via ground wires in a down-bonding manner. In other words, the lead frame provides the leads and a peripheral area of the die pad as wire-bonding regions for electrically connecting the bonding wires.
When the chip is electrically connected to the lead frame, since the lead frame is primarily made of copper and the bonding wires are primarily made of gold that has poor bondability with copper, a silver layer is usually in advance plated on the wire-bonding regions (such as the leads) of the lead frame, such that an eutectic structure is formed by the gold bonding wires and the silver layer on the wire-bonding regions during the wire-bonding process, and thus the bonding wires are bonded and connected to the lead frame. However, due to the weak adhesion between the silver layer and the encapsulant, it is easy to cause delamination therebetween by thermal stress in subsequent fabrication processes and even cause wire cracks or breakage.
Particularly for the QFN semiconductor package, it is characterized in not having outer leads that are used to establish external electrical connection in the conventional quad flat package (QFP), and thus the size of the QFN package can be relatively reduced. As shown in FIG. 1A of the QFN semiconductor package 1, bottom surfaces of a die pad 11 and leads 12 of a lead frame 10 are all exposed from an encapsulant 15, such that heat generated by a semiconductor chip 13 that is mounted on the die pad 11 and electrically connected to the leads 12 via bonding wires 14 can be effectively dissipated out of the QFN semiconductor package 1, and also the QFN semiconductor package 1 can be directly electrically connected to an external device such as a printed circuit board (not shown) via the exposed surfaces of the leads 12.
As shown in FIGS. 1B and 1C that are partial enlarged views of a bonding wire 14 for electrically connecting the semiconductor chip to the lead frame, since only one surface of the QFN lead frame is encapsulated by the encapsulant 15, during a molding process, delamination would be easily incurred between the encapsulant 15 and the silver layer on the lead 12 due to thermal stress, thereby leading to cracks or breakage of the bonding wire 14 and degrading the package reliability.
In light of the foregoing drawbacks, U.S. Pat. Nos. 6,208,020, 6,338,984, and 6,483,178 have proposed a structure with grooves or holes being formed on the leads of the lead frame to improve the adhesion between the lead frame and the encapsulant.
A lead-frame-based semiconductor package disclosed in U.S. Pat. No. 6,483,178 is shown in FIG. 2. This semiconductor package is a QFN package 2 comprising a die pad 21 having an exposed bottom surface; a chip 23 attached to the die pad 21; a plurality of leads 22 formed around the die pad 21; bonding wires 24 connected between the chip 23 and the leads 22; and an encapsulant 25 for encapsulating the leads 22, the chip 23, the bonding wires 24, and the die pad 21, wherein the bottom surface of the die pad 21 and bottom and outer surfaces of the leads 22 are exposed from the encapsulant 25. A characteristic feature of this semiconductor package 2 is to form at least one bolt hole 26a in each of the leads 22 and allow the encapsulant 25 to fill the bolt holes 26a. Each of the bolt holes 26a comprises two cylindrical holes 261a, 262a, wherein the upper cylindrical hole 261a has smaller axial coverage than the lower cylindrical hole 262a. This difference in coverage allows the encapsulant 25 filling the bolt holes 26a to be firmly engaged with the leads 22, such that the leads 22 are strongly fixed in the encapsulant 25.
In accordance with the development of light-weight and small-profile electronic devices, a fine-pitch and small-size lead frame has been widely used. However, there is no sufficient area on small leads of such lead frame to accommodate grooves or holes, and the grooves and holes are also difficult to be fabricated. Moreover, the rigidity of the small leads would be undesirably reduced with the grooves or holes being formed thereon, making bonding wires hard to be bonded to the leads. Conventionally, the grooves or holes are formed outside wire-bonding areas of the leads and thus not effective to solve the problem of delamination between the silver layer on the wire-bonding areas and the encapsulant.
U.S. Pat. No. 5,960,262 has disclosed a wire-bonding method for reinforcing a bonding structure by forming a stud bond over a stitch bond of a bonding wire. This wire-bonding method is shown in FIGS. 3A to 3F.
First referring to FIGS. 3A and 3B, a wire bonder is prepared, which comprises a capillary 34 for accommodating a gold wire (bonding wire) 32, and a damper 36 for clamping and releasing the gold wire 32. A free air ball (FAB) is formed at a front end of the gold wire 32 in the capillary 34 by a conventional ball-sintering process and is pressed on a corresponding input/output (I/O) pad 300 of a semiconductor chip so as to form a ball bond (generally referred to as a first bond) bonded to the I/O pad 300. Then referring to FIG. 3C, the capillary 34 is moved to draw the gold wire 32 to a lead 31 of a lead frame to form a stitch bond (generally referred to as a second bond) on a predetermined position of the lead 31, and then the gold wire 32 is cut from the capillary 34. Subsequently referring to FIGS. 3D to 3F, a stud bond 37 made of the same material as the gold wire 32 is implanted on the stitch bond so as to reinforce the bonding strength between the stitch bond and the lead 31.
However, the provision of stud bond on the second bond (stitch bond) can only enhance the bonding strength between the second bond and the lead frame, such that a neck portion of the gold wire near the second bond becomes relatively weaker in structural strength and is easily subject to cracks. Moreover, highly precise movement of the capillary is required to form the stud bond. This undesirably prolongs the fabrication time, increases the fabrication cost, and causes difficulty in fabrication. Furthermore, during cutting the gold wire after the stud bond is formed, a cutting position of the gold wire depends on the movement of capillary and is not easily controlled. This causes a portion of the gold wire remaining on the capillary to be varied in length, and thus affects the shape of FAB fabricated by the next ball-sintering process and makes the size of the ball bond not uniformed.
Therefore, the problem to be solved here is to provide a semiconductor package with a lead frame, which can overcome the above drawbacks in the prior art.